ERROR: [VRFC 10-1145] non-net port d_x cannot be of mode inout error in verilog

I am writing a code for finding a path by north last routing in NOC. I have not declared any of the inputs as inout but still the error given below is shown. This error is popping up for literally all of the codes I write. Where is the problem?

I am providing my code and testbench here.

code:

timescale 1ns / 1ps



module mesh  (
input  [15:0] a,
input  [1:0] c_x,
input  [1:0] c_y ,
output [3:0] port
    ); 
 
  reg d_x=0,d_y=0,s_x=0,s_y=0;
    
 always @ (a or c_x or c_y)//when cx or cy changes, this loop happens 
 begin
  d_x=a[1:0];// x coordinate of destination address
  d_y=a[3:2];//y coordinate of destination address
 s_x=a[5:4];// x coordinate of source addres
  s_y=a[7:6];// y coordinate of source addres
 
comp u1(
    .a(a),
    .c_x(c_x),
    .c_y(c_y),
    .port(port)
);
  
     
       end                   
endmodule

testbench:

`timescale 1ns / 1ps


module north_tb(
reg  [15:0] a,
reg [1:0] c_x,
reg [1:0] c_y ,
wire [3:0] port
 
    );
    
 mesh u1(
 .a(a),
 .c_x(c_x),
 .c_y(c_y),
 .port(port)
 );
    
  initial 
  begin  
    a[15:0] = 16'b100110101001010;//
    c_x=2'b01;
    c_y =2'b00;
    #5
    c_x=2'b01;
    c_y =2'b01;
    #5
    c_x=2'b01;
    c_y =2'b10;
    #5
    c_x=2'b10;
    c_y =2'b10;
    #5
          
    
 
                  
  
  $finish;                  
                    
                    
                    


end
endmodule

following is the error message:

ERROR: [VRFC 10-1145] non-net port d_x cannot be of mode inout [D:/Vivado/northlast/northlast.srcs/sim_1/new/comp_tb.v:4]
ERROR: [VRFC 10-1145] non-net port d_y cannot be of mode inout [D:/Vivado/northlast/northlast.srcs/sim_1/new/comp_tb.v:5]
ERROR: [VRFC 10-1145] non-net port c_x cannot be of mode inout [D:/Vivado/northlast/northlast.srcs/sim_1/new/comp_tb.v:6]
ERROR: [VRFC 10-1145] non-net port c_y cannot be of mode inout [D:/Vivado/northlast/northlast.srcs/sim_1/new/comp_tb.v:7]
ERROR: [VRFC 10-1040] module comp_tb ignored due to previous errors [D:/Vivado/northlast/northlast.srcs/sim_1/new/comp_tb.v:3]

>Solution :

The testbench problem is that testbench’s generally don’t have ports.
The posted testbench has ports and the tools don’t like the way the rest of the testbench is trying to use them.

In a testbench, when driving or reading signals/variables to/from the design under test, declare those signals locally.

Like this:

module north_tb();    

  // local signals
  reg  [15:0] a  ;
  reg [1:0] c_x  ;
  reg [1:0] c_y  ;
  wire [3:0] port;  
    
 mesh u1(
 .a(a),
 .c_x(c_x),
 .c_y(c_y),
 .port(port)
 );
  initial 
  begin  
    a[15:0] = 16'b100110101001010;//
    c_x=2'b01;
    c_y =2'b00;
    #5
    c_x=2'b01;
    c_y =2'b01;
    #5
    c_x=2'b01;
    c_y =2'b10;
    #5
    c_x=2'b10;
    c_y =2'b10;
    #5

  $finish;                  
end
endmodule

The post has a problem in the mesh module. It instantiates a module called comp which is not provided in the post. I don’t think this is the problem that triggered post though.

I think the problem is trying to have ports on the testbench module, and expecting them to function as local signals.

Could in be that all the code you write have ports on the testbenches?

In the mesh module this statement is bad for a couple of reasons.

 always @ (a or c_x or c_y)//when cx or cy changes, this loop happens

A recommendation is to replace it with

always @ (*)

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