I am starting in FPGA coding, and one of my first exercises is to code a full adder. I am using SystemVerilog to code within Vivado. My take on this is as follow:
`timescale 1ns/10ps module challenge ( input wire [2:0] SW, output logic [1:0] LED ); assign LED=SW^SW^SW; // Write the code for the Sum assign LED=(SW&SW)|((SW^SW)&SW); // Write the code for the Carry endmodule // challenge
`timescale 1ns/100ps module tb; logic [2:0] SW; logic [1:0] LED; challenge u_challenge (.*); // Stimulus initial begin $printtimescale(tb); SW = '0; for (int i = 0; i < 8; i++) begin $display("Setting switches to %3b", i[2:0]); SW = i[2:0]; #100; end $display("PASS: logic_ex test PASSED!"); $stop; end logic [2:0] sum; assign sum = SW + SW + SW; // Checking always @(SW, LED) begin if (sum !== LED) begin $display("FAIL: Addition mismatch"); $stop; end end endmodule // tb
No matter what I put from
LED (any combination of SW,SW,SW), I will always have my
LED values set to X.
Is there a problem with my definition of
Your definition of
SW looks fine.
I removed the
$stop calls from your code so the simulation would run to completion. Using
$stop halts your simulation and sets it to interactive mode. Perhaps Vivado is waiting for you to enter commands before it updates your output.
I copied your code onto EDA Playground, and it runs fine. I don’t see X in the waveforms.
Here is the output I see:
Setting switches to 001 FAIL: Addition mismatch Setting switches to 010 Setting switches to 011 FAIL: Addition mismatch FAIL: Addition mismatch Setting switches to 100 FAIL: Addition mismatch Setting switches to 101 FAIL: Addition mismatch FAIL: Addition mismatch Setting switches to 110 FAIL: Addition mismatch Setting switches to 111 FAIL: Addition mismatch FAIL: Addition mismatch PASS: logic_ex test PASSED!