Assigning 16 bit to 4 bit

I have this binary to bcd code. In the end I get 4 4bit bcd numbers. Basically I can say these are hex numbers.

module bin2bcd(
   input [13:0] bin,
   output reg [15:0] bcd );
   
integer i;
    
always @(bin) begin
    bcd=0;          
    for (i=0;i<14;i=i+1) begin
        if (bcd[3:0]   >= 5) bcd[3:0] =   bcd[3:0]   + 3;
        if (bcd[7:4]   >= 5) bcd[7:4] =   bcd[7:4]   + 3;
        if (bcd[11:8]  >= 5) bcd[11:8] =  bcd[11:8]  + 3;
        if (bcd[15:12] >= 5) bcd[15:12] = bcd[15:12] + 3;
        bcd = {bcd[14:0],bin[13-i]};
    end
end
endmodule

I need to display 4 numbers separately in the seven segment of the FPGA. And I have this seven segment code.

module hex2seg(
    input [3:0] hex,
    output reg [6:0] seg );
    
    always @(*) begin
        case(hex)
            4'h0: seg = 7'b1000000;    // "0"  
            4'h1: seg = 7'b1111001;    // "1" 
            4'h2: seg = 7'b0100100;    // "2" 
            4'h3: seg = 7'b0110000;    // "3" 
            4'h4: seg = 7'b0011001;    // "4" 
            4'h5: seg = 7'b0010010;    // "5" 
            4'h6: seg = 7'b0000010;    // "6" 
            4'h7: seg = 7'b1111000;    // "7" 
            4'h8: seg = 7'b0000000;    // "8"  
            4'h9: seg = 7'b0010000;    // "9"
            4'hA: seg = 7'b0001000;    // "A"
            4'hB: seg = 7'b0000011;    // "b"
            4'hC: seg = 7'b1000110;    // "C"
            4'hD: seg = 7'b0100001;    // "d"
            4'hE: seg = 7'b0000110;    // "E"
            4'hF: seg = 7'b0001110;    // "F"
            default: seg = 7'b1000000; // "0"
        endcase
    end 
endmodule

Somehow, I must assign this [15:0]bcd to [3:0]hex. Is there way to do that?

I have tried a clock divider to show two segments simultaneously.

module clk1 (
    input clk,
    output X );

reg [12:0] counter;

always @ (posedge clk)  begin
    counter <= counter + 1;
end
 
assign Y = counter[12]; 
endmodule

Then in top module:

assign an[2] =  Y ;
assign an[3] = ~Y ; 

But still don’t know how to assign 16bit bcd to seven segment code.

>Solution :

To assign a 16-bit BCD number to a 7-segment display on an FPGA, you will need to multiplex the display since a single 7-segment display can only show one hex digit (4 bits) at a time. Your task is to display each 4-bit chunk of the 16-bit number on different segments of the display one after the other.

Given your current bin2bcd module, which converts a binary number to a 16-bit BCD format, and the hex2seg module that converts a 4-bit hex number to the 7-segment format, you need to add a mechanism to cycle through each 4-bit chunk of the BCD number and send it to the hex2seg module.

Here’s a basic outline of what you need to do in your top module:

Divide the 16-bit BCD Number: Split the 16-bit BCD output into four 4-bit groups. Each group will represent a single digit to be displayed on one of the segments of the 7-segment display.

Multiplexing: Implement a multiplexer that cycles through each 4-bit group and sends it to the hex2seg module. The multiplexer can be controlled by a clock divider (like the one you have in your clk1 module) to change the displayed digit at regular intervals. This will create the illusion that all digits are displayed simultaneously.

Display Control: Use the output from your clock divider to control which segment of the 7-segment display is active at any given time.

Here’s a simplified version of how you can implement this in Verilog:

    module top_module(
    input clk,             // Clock input
    input [13:0] bin,      // Binary input
    output [6:0] seg,      // 7-segment output
    output [3:0] an        // Anode signals for 4 digits
    );

wire [15:0] bcd;
bin2bcd my_bin2bcd(bin, bcd);

wire [1:0] mux_select;
clk_divider my_clk_divider(clk, mux_select);

reg [3:0] hex;
always @(*) begin
    case (mux_select)
        2'b00: hex = bcd[3:0];   // Least significant digit
        2'b01: hex = bcd[7:4];
        2'b10: hex = bcd[11:8];
        2'b11: hex = bcd[15:12]; // Most significant digit
    endcase
end

hex2seg my_hex2seg(hex, seg);

// Control the anode signals based on mux_select
assign an = (mux_select == 2'b00) ? 4'b1110 :
            (mux_select == 2'b01) ? 4'b1101 :
            (mux_select == 2'b10) ? 4'b1011 :
            4'b0111;

endmodule

module clk_divider(
    input clk,
    output reg [1:0] div_out
);

// Clock division logic to cycle through 0 to 3 (2-bit binary)
always @(posedge clk) begin
    div_out <= div_out + 1;
end

endmodule

In this setup, the clk_divider module generates a 2-bit output (mux_select) that cycles from 0 to 3. This output is used to select which 4-bit group from the 16-bit BCD number is sent to the hex2seg module. The an output controls which segment is active based on the mux_select value.