Problem on HDLBits: Exams/m2014 q6c, stuck at gnd

Problem : https://hdlbits.01xz.net/wiki/Exams/m2014_q6c

Here is my code

module top_module (
    input [6:1] y,
    input w,
    output Y2,
    output Y4);

    parameter A = 000001, B = 000010, C = 000100, D = 001000, 
    E = 010000, F = 100000;
    reg [2:0] next_state;
    
    always @(*) begin
        casez(y)
        6'b000001 : next_state <= w ? A : B;
        6'b00001z : next_state <= w ? D : C;
        6'b0001zz : next_state <= w ? D : E;
        6'b001zzz : next_state <= w ? A : F;
        6'b01zzzz : next_state <= w ? D : E;
        6'b1zzzzz : next_state <= w ? D : C;
        default : next_state <= A;
        endcase
    end

    assign Y2 = next_state == B;
    assign Y4 = next_state == D;
endmodule

I can’t understand why this code can’t solve the problem. Using this code, Y2 and Y4 are stuck at GND. I think there’s a problem with "casez", but I am not sure.

Could you give me a correct answer and tell me the reason?

>Solution :

There are two major bugs in your code. When I run the simulation on HDLBits, I see many warning messages which directly point to the problems.

The 1st problem is that the state parameter values are decimal format, not binary format. You need to add the 6'b prefix to all the values:

parameter A = 6'b000001, B = 6'b000010, C = 6'b000100, D = 6'b001000, 
    E = 6'b010000, F = 6'b100000;

The 2nd problem is the width of the next_state signal. It is only 3 bits wide, but it must be 6 bits wide in order to assign a 6-bit value to it. Use:

reg [5:0] next_state;

These changes fix the problem mentioned in the question: Y2 and Y4 are no longer stuck at GND. The changes also eliminate all warning messages.

Going forward, you really need to create your own testbench to debug further problems. Unfortunately, the HDLBits online interface to the exercises like the one in the question does not allow you to see waveforms of internal signals.