Advertisements I am trying to build a docker container using a makefile: up_build_dev: @echo "Stopping docker images (if running…)" docker-compose down @echo "Building (when required) and starting docker images…" DB_USER=backend DB_PASSWORD=password DB_ROOT_USER=root DB_ROOT_PASSWORD=password DB_NAME=my_db DB_PORT=3306 DB_HOST=mysql LISTEN_PORT=80 HOST_PORT=8080 ENV=dev docker-compose up –build -d @echo "Docker images built and started!" The environment variables are not passed,… Read More Makefile not passing env variables to docker compose command

Advertisements I have two lists, both with N elements: SRC = a/b/foo a/b/bar a/b/moo DST = a/c/fii a/c/bir a/c/mee Is there a way to set a rule that takes the i-th element of SRC as the prerequisite of the i-th element of DST? I just need to copy, so what I am thinking of is… Read More How to instruct Make to copy the i-th file of a list to the i-th path of another list?

Advertisements I’ve discovered the Makefile file function a few days ago and it’s perfect for what I need to do…. except there is something I can’t make sense of. See this trivial Makefile: FILENAME := test.txt CONTENT := whatever all: clean ifneq (1, $(CLEAN)) rm -f $(FILENAME) endif $(file > $(FILENAME),$(CONTENT)) ls $(FILENAME) clean: ifeq… Read More Interaction of Makefile `file` function with `rm`

Advertisements I have a Makefile such that one of the targets creates a .env file, which is read in another target. So, since the file is created dynamically, I can’t include it at the top of the Makefile. I tried the method using export and xargs, as described here, but it doesn’t work. Here’s my… Read More Reading dotenv file within a target in a Makefile

Advertisements Considering the general rule form: output_file_name: dep_file_name1, dep_file_name_2, …, dep_file_name_n recipe and assuming in one’s hypothetical makefile with no phony targets ever, every dep_file_name_x is always a file name and often also another rule (ie. it is another rule’s output_file_name), my question is: Hitting any of many such rules, does make only check the… Read More With a rule's prerequisite both a file and another rule, is only the file date checked, or always first that "sub rule" itself?

Advertisements Suppose I have a recipe that accepts a group of prerequisites: prereqs=a b c $(prereqs): bash configure.sh And I would like any of a b c to trigger bash configure.sh, but I want it to be run only once. I am aware of other ways to solve this problem. I know there are decorators… Read More How does one set up a group recipe that gets run only once?

Advertisements Consider the following Makefile as an MWE: ################################################################### # first bunch ################################################################### FORTRAN1 = ifort -c PATH1 = sub/ FILE1 = first.f90 SOURCE1 = $(FILE_TEST:%=$(PATH1)%) OBJECT1 = $(addprefix lnk/,$(addsuffix .o,$(basename $(FILE1)))) ################################################################### #second bunch ################################################################### FORTRAN2 = ifort -traceback -c PATH2 = sub/ FILE2 = second.f90 SOURCE2 = $(FILE2:%=$(PATH2)%) OBJECT2 = $(addprefix lnk/,$(addsuffix .o,$(basename… Read More What causes a conflict between pattern rules in the Makefile below?

Advertisements I am trying to create a makefile pattern to transform the source files articles/*/source.txt to target files articles/*/target.html, where * is one and/or multiple single-level directories with unknown names. Each source.txt file should when running make generate a target.html file in the same corresponding directory. I was trying to use $(wildcard article/*) to create… Read More Pattern match for files in multiple subdirectories where the names of the subdirectories is unknown

Advertisements I have a Makefile like this bin: mkdir -p bin bin/kustomize: bin curl -fsSL "https://raw.githubusercontent.com/kubernetes-sigs/kustomize/master/hack/install_kustomize.sh" | bash -s bin When I run make bin/kustomize it tries to download it, every time, even though it is already there. I would expect that make doesn’t want to run that target. When I remove the dependency to… Read More make runs target even though file already exists

Advertisements I have the following Makefile: TARGET = main.elf BUILD_DIR = build SRC_DIR = src CC = arm-none-eabi-gcc -std=gnu17 CXX = arm-none-eabi-g++ -std=c++17 LINKER = arm-none-eabi-g++ OBJDUMP = arm-none-eabi-objdump OBJCOPY = arm-none-eabi-objcopy INCLUDES = -I./src/inc \ -I./src/usys/inc SRC_FILES_C = $(SRC_DIR)/usys/startup.c \ $(SRC_DIR)/usys/usys.c SRC_FILES_CXX = $(SRC_DIR)/main.cpp LINKER_FILE = $(SRC_DIR)/usys/flash.ld CFLAGS = -Wall -Wextra -g3 -O0 CFLAGS… Read More Makefile results in multiple definition errors