8 bit serial to parallel shifter in vhdl

I programmed an 8-bit shifter in vhdl:

entity 8b is 
  port(s, clk : in std_logic; p : out std_logic_vector (7 downto 0)); 
end entity; 

architecture arch of 8b is 
  Signal iq : std_logic_vector (7 downto 0); 
begin 
  process(clk) 
  begin 
    if rising_edge(clk) then 
      iq(7) <= s;
      iq(6 downto 0) <= iq(7 downto 1); 
    end if; 
  end process; 
  p <= iq; 
end architecture; 

The idea is that I’m taking input and giving it to my first D-FF.
Then over the next 7 cycles, the other Flip Flops get the other serial inputs which will be given to the parallel output p.

However, I’m not sure if this logic is flawed because this is the solution we got for this exercise:

architecture behavior of 8b is
  signal p_intern : std_logic_vector(7 downto 0);
begin
  P <= p_intern;
  process(CLK)
  begin
    if rising_edge(CLK) then
      p_intern <= p_intern(6 downto 0) & S;
    end if;
  end process;
end architecture;

But I don’t get the p_intern <= p_inter(6 downto 0) & S; part.

Can someone please explain the logic behind this and if my version is also valid?

>Solution :

The only difference between the two implementations seem to be the lines

iq(7) <= s;
iq(6 downto 0) <= iq(7 downto 1); 

vs.

p_intern <= p_intern(6 downto 0) & S;

and that iq is named p_intern. Let’s assume they are both named iq for the sake of comparison.

Let’s see what they are doing:

The first implementation (yours) assigns to the positions of iq:

7     6     5     ... 1     0
s     iq(7) iq(6) ... iq(2) iq(1)

The second implementation (the solution) assigns

7     6     5     ... 1     0
iq(6) iq(5) iq(4) ... iq(0) s

Where iq(6 downto 0) & s means "concatenate s to the right of iq(6 downto 0)".

So they are not equivalent. Your implementation shifts in the values from the left, and the solution shifts in the values from the right. Which one is correct depends on the specification (presumably the solution is correct).