Expected a constant as index error in Verilog

I’m trying to do some projects on Verilog and I have a problem with constant index errors.

integer k=32;
reg[k-1:0] inputs;

In this part, the Verilog compiler gives me "Expected a constant as index error in Verilog" message.
I must use integer k in this project. How can I solve this problem?

>Solution :

integer is a variable type. As the error message states, you need a constant type, such as parameter:

parameter k=32;
reg[k-1:0] inputs;