I can't fill with 0 a reg array in verilog with a for loop in an always block

The error I get for the code below is:

Procedural assignment to a non-register j is not permitted, left-hand
side should be reg/integer/time/genvar.

When I do W_E[0] = 0, W_E[1] = 0 etc, I don’t get any error.

genvar j;
reg W_E [31:0];
always @(*)begin
    // Wrting Data to a specific register
    for (j = 0; j < 32; j = j + 1)begin
        W_E[j] = 0;
    end
end

>Solution :

The problem is that you are using a genvar in a for loop. Use genvar only when you are actually using a generate statement, per the Verilog LRM, IEEE Std. 1364-2005, section 12.4.1:

The genvar is used as an integer during elaboration to evaluate the generate loop and create instances of the
generate block, but it does not exist at simulation time. A genvar shall not be referenced anywhere other
than in a loop generate scheme.

Change the type of j to an integer and it will work:

integer j;
reg W_E [31:0];
always @(*)begin
    // Wrting Data to a specific register
    for (j = 0; j < 32; j = j + 1)begin
        W_E[j] = 0;
    end
end