# Syntax error verilog defining module iverilog

I’m getting a syntax error at 11 line Full adder using xor and mux2x1 module xormux(x1, x2, x3, y1, y2); input x1, x2, x3; output y1, y2; wire w1, w2; xor gate1(w1, x1, x2); xor gate2(y1, w1, x3); mux2x1 gate3(y2, w1, x3, x2); endmodule module xor(output o, input i1, i2); assign o = i1 ^… Read More Syntax error verilog defining module iverilog