What is the meaning of "= |" in Verilog?

Can someone please tell me what is the meaning of "= |" in these Verilog lines:

wire result;
wire [NUM_BITS-1:0] pterms;
assign result = | pterms;

If it means assign result = result | pterms, then does this mean that it does an OR operation between the result wire and pterms[0]?

>Solution :

No, in your code, | is the reduction-OR operator which does a bitwise OR of all the bits of pterms and assigns the 1-bit result to the result wire. Refer to IEEE Std 1800-2017, section 11.4.9 Reduction operators.

If pterms is 4 bits, then the assignment is the same as:

assign result = pterms[3] | pterms[2] | pterms[1] | pterms[0];

Here is a running example:

module tb;

parameter NUM_BITS = 4;
wire result;
logic [NUM_BITS-1:0] pterms;
assign result = | pterms;

initial begin
    for (int i=0; i<16; i++) begin
        #1 pterms = i;
        #1 $displayb(pterms,,result);
    end
end

endmodule

Displays:

0000 0
0001 1
0010 1
0011 1
0100 1
0101 1
0110 1
0111 1
1000 1
1001 1
1010 1
1011 1
1100 1
1101 1
1110 1
1111 1