Syntax error in conditional case statement

I’m trying to make a controller, but it keeps giving me the following error:

./controller.v:46: syntax error
./controller.v:47: Syntax in assignment statement l-value.
./controller.v:46: error: Incomprehensible case expression.
./controller.v:60: syntax error
./controller.v:61: Syntax in assignment statement l-value.
./controller.v:60: error: Incomprehensible case expression.

I still don’t know when to use the begin and end correctly, but here’s the code:

module controller (
    input zero, clk, rst,
    input [2:0] opcode, phase,
    output reg sel, rd, ld_ir, halt, inc_pc, ld_ac, wr, ld_pc, data_e
);


always @(posedge clk or negedge rst)
    case (phase)
        3'd0: 
        begin
            sel = 1'b1;
            rd = 1'b0;
            ld_ir = 1'b0;
            halt = 1'b0;
            inc_pc = 1'b0;
            ld_ac = 1'b0;
            ld_pc = 1'b0;
            wr = 1'b0;
        end
        3'd1: rd = 1'b1;
        3'd2: ld_ir = 1'b1;
        3'd3: ;
        3'd4:
        begin
            sel = 1'b0;
            rd = 1'b0;
            ld_ir = 1'b0;
            halt = (opcode == 3'b000)? 1'b1 : 1'b0;
            inc_pc = 1'b1;
            ld_ac = 1'b0;
            ld_pc = 1'b0;
            wr = 1'b0;
            data_e = 1'b0;
        end
        3'd5:
        begin
            sel = 1'b0;
            ld_ir = 1'b0;
            halt = 1'b0;
            inc_pc = 1'b1;
            ld_ac = 1'b0;
            ld_pc = 1'b0;
            wr = 1'b0;
            data_e = 1'b0;
            case (opcode):
                3'b010, 3'b011,3'b100, 3'b101: rd = 1'b1;
                default: rd = 1'b0;
            endcase
        end
        3'd6:
        begin
            inc_pc = ((opcode == 3'b001) && zero ) ? 1'b1 : 1'b0;
            ld_pc = (opcode == 3'b111) ? 1'b1 : 1'b0;
            data_e = (opcode == 3'b110) ? 1'b1 : 1'b0;
        end
        default: 
        begin
            inc_pc = 1'b0;
            case (opcode):
                3'b010, 3'b011,3'b100,3'b101: ld_ac = 1'b1;
                default: ld_ac = 0;
            endcase
            wr = (opcode == 3'b110) ? 1'b1 : 1'b0;
        end
    endcase
endmodule

Apart from the logic of my code, I’d like to know why does it give me these errors.

>Solution :

The problem is that you should not use a colon at the end of the case lines. You should only use colons inside the case statement after the case items. For example, your 1st case statement should be:

case (opcode)
    3'b010, 3'b011,3'b100, 3'b101: rd = 1'b1;
    default: rd = 1'b0;
endcase

The same applies to the other case statement. Making these changes, I no longer get syntax errors.

Your usage of begin/end looks correct.