How to print output and create a .vcd file?

June 3, 2023

I am a beginner, and I am learning VerilogHDL. I am trying to implement a simple NOT GATE code. What I want to do is print the output of the simulation with the $monitor() function, and I want to generate a .vcd file to be able to simulate it with GTKwave. I am using the Icarus Verilog (iverilog) Compiler. Below you will find the code.

Code for NOT GATE:

module notagate(
    input a,
    output y
);

always @ (a) begin
    if(a == 1'b0) begin
        y = 1'b1;
    end
    else if(a == 1'b1) begin
        y = 1'b0;
    end
endmodule

Code for NOT GATE TESTBENCH:

module notgate_tb;

    reg a,
    wire y;

    notgate_tb uut(y, a);

        initial begin
        $dumpfile("notgate_tb.vcd");
        $dumpvars(0,notgate_tb);
        $monitor("%t | a = %d | y = %d", $time, a, y);

        a = 0;
        # 1 a = 1;
        # 1 a = 0;
    end
endmodule

When I run the following command:

iverilog -o notgate notgate_tb.v notgate.v

I get the following errors:

notgate_tb.v:4: syntax error
notgate_tb.v:1: error: Syntax error in variable list.
notgate.v:13: syntax error
I give up.

Why am I getting these errors, and how can I fix the code?

>Solution :

There are several syntax errors.

In the notgate_tb module, change the comma to a semicolon:

    reg a;

Change the uut instance line to use notgate, not notgate_tb. And, use connection-by-name, not connection-by-order.

In the notgate module, add a closing end statement before endmodule,
declare y as reg since you assign to it inside an always block (procedural assignment), and change the module name to notgate. This code fixes all errors:

module notgate(
    input a,
    output reg y
);

always @ (a) begin
    if(a == 1'b0) begin
        y = 1'b1;
    end
    else if(a == 1'b1) begin
        y = 1'b0;
    end
end
endmodule

module notgate_tb;

    reg a;
    wire y;

    notgate uut (.y(y), .a(a));

    initial begin
        $dumpfile("notgate_tb.vcd");
        $dumpvars(0,notgate_tb);
        $monitor("%t | a = %d | y = %d", $time, a, y);

        a = 0;
        # 1 a = 1;
        # 1 a = 0;
    end
endmodule

Here is the output I get:

VCD info: dumpfile notgate_tb.vcd opened for output.
                   0 | a = 0 | y = 1
                   1 | a = 1 | y = 0
                   2 | a = 0 | y = 1