Home Is there a way to compile a bunch of C source code one by one with a Makefile?

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Is there a way to compile a bunch of C source code one by one with a Makefile?

June 2, 2022

I have created a Makefile along with some C source code files and a header file (.h).

NAME = libft.a

SRCS = ft_isalnum.c ft_isalpha.c ft_isascii.c ft_isdigit.c ft_isprint.c ft_strlen.c ft_bzero.c ft_memcpy.c ft_memset.c ft_memmove.c ft_strlcpy.c ft_strlcat.c ft_toupper.c ft_tolower.c ft_strchr.c ft_strrchr.c ft_strncmp.c ft_memchr.c ft_memcmp.c ft_strnstr.c ft_atoi.c ft_calloc.c ft_strdup.c ft_substr.c ft_strjoin.c ft_strtrim.c ft_split.c ft_itoa.c ft_strmapi.c ft_striteri.c ft_putchar_fd.c ft_putstr_fd.c ft_putendl_fd.c ft_putnbr_fd.c

SRC_BONUS = ft_lstnew.c ft_lstadd_front.c ft_lstsize.c ft_lstlast.c ft_lstadd_back.c ft_lstdelone.c ft_lstclear.c ft_lstiter.c ft_lstmap.c

OBJECTS = $(SRCS:.c=.o)

OBJ_BONUS = $(SRC_BONUS:.c=.o)

CFLAGS = -Wall -Wextra -Werror

all: $(NAME)

$(NAME): $(OBJECTS)
        ar rc $(NAME) $(OBJECTS)

$(OBJECTS): $(SRCS)
        gcc $(CFLAGS) -c $(SRCS)

$(OBJ_BONUS): $(SRCS) $(SRC_BONUS)
        gcc $(CFLAGS) -c $(SRCS) $(SRC_BONUS)

bonus: $(OBJECTS) $(OBJ_BONUS)
        ar rc $(NAME) $(OBJECTS) $(OBJ_BONUS)

I have to create object files with those C source code files, then use those object files o create a static library (.a).

So, I was wondering if there is a way to compile each source code file one by one instead of compiling all of those files in one step?

gcc -Wall -Wextra -Werror -c ft_isalnum.c ft_isalpha.c ft_isascii.c ft_isdigit.c ft_isprint.c ft_strlen.c ft_bzero.c ft_memcpy.c ft_memset.c ft_memmove.c ft_strlcpy.c ft_strlcat.c ft_toupper.c ft_tolower.c ft_strchr.c ft_strrchr.c ft_strncmp.c ft_memchr.c ft_memcmp.c ft_strnstr.c ft_atoi.c ft_calloc.c ft_strdup.c ft_substr.c ft_strjoin.c ft_strtrim.c ft_split.c ft_itoa.c ft_strmapi.c ft_striteri.c ft_putchar_fd.c ft_putstr_fd.c ft_putendl_fd.c ft_putnbr_fd.c

Is the same exact thing to compile every source code file at once or doing it one by one?

This obviusly cannot happen with the library, I need just one static library to have all those functions, so I must use all object files to create it.

gcc -Wall -Wextra -Werror -c ft_isalnum.c ft_isalpha.c ft_isascii.c ft_isdigit.c ft_isprint.c ft_strlen.c ft_bzero.c ft_memcpy.c ft_memset.c ft_memmove.c ft_strlcpy.c ft_strlcat.c ft_toupper.c ft_tolower.c ft_strchr.c ft_strrchr.c ft_strncmp.c ft_memchr.c ft_memcmp.c ft_strnstr.c ft_atoi.c ft_calloc.c ft_strdup.c ft_substr.c ft_strjoin.c ft_strtrim.c ft_split.c ft_itoa.c ft_strmapi.c ft_striteri.c ft_putchar_fd.c ft_putstr_fd.c ft_putendl_fd.c ft_putnbr_fd.c

>Solution :

Yes this is possible.

With something like this

SRC += $(wildcard src/*.c)

OBJECTS += $(SRC:%.c=%.o)

INCLUDE += -Iinclude

NAME = test

binary: $(OBJECTS)
    gcc -o $(NAME) $(OBJECTS)

%.o: %.c
    gcc -o $@ -c $< $(INCLUDE)

You have to adapt this to your makefile of course.

The key part is the last target which is executed for each *.o (and each *.o depends on its *.c file, so this *.o will only be compiled when it’s older than the *.c file).
The output from a call to that makefile in a project with two files main.c and other.c could look like this:

>$ make binary 
gcc -o src/other.o -c src/other.c -Iinclude
gcc -o src/main.o -c src/main.c -Iinclude
gcc -o test src/other.o src/main.o

You can find some tips that might be helpful for you here:
http://nuclear.mutantstargoat.com/articles/make/

PS:

I’d suggest using source and include directories (commonly "src" and "include") and an output directory ("build" or "out" are common here). Makes your life and makefile easier.