I’m trying to learn how to use Make! So I have this simple Makefile, all: main other main: main.c other.o gcc main.c -o main echo "Compiled main.exe" other: other.o other.c: touch $@ echo "int main(){return 0;}" > $@ echo "Created other.c" other.o: other.c gcc other.c -o other.o echo "Compiled other.o" clean: rm -f main.exe other.o… Read More Why does Make automatically execute a cc command?

I have python script inside container which needs two arguments to run. I tried to run the script using Makefile. For this I made make command: .PHONY: deploy deploy: @docker exec -it ecosystem python3 deployment/deploy.py $(filter-out $@,$(MAKECMDGOALS)) When I run make deploy server project, the script works, but when it finishes I get the following… Read More Make with arguments

I have the following simplified Makefile: foo-%: dep-% @echo in foo $* bar-%: dep-% dep-%: @echo in dep $* make dep-aa works. What is interesting is that while make foo-aa works, make bar-aa does not, even though it has the same dependency on dep-%. Why is that? And how do you work around it? $… Read More why does make not expand stem in dependency when there is no action to take?

When I compile my C program with make I get an error. I’ve been developing this project for a few days now and everything compiled fine until I needed to add an external file (semaphore_v2.h). I don’t know if I’m importing it incorrectly or what but when I try to compile the project with it… Read More How to solve Makefile error multiple definition of

For an assignment in one of my classes we need to create a makefile for our C program that’s more complex than just compile: gcc whatever. I believe we’re expected to do something like this: outputname: file1.o file2.o file3.o file4.o gcc -o outputname file1.o file2.o file3.o file4.o clean: rm -f outputname file1.o file2.o file3.o file4.o… Read More C Makefile – How to avoid redundant mentions of file names

Problem I am trying to use if and else statement in a Makefile but all the things I tried are not working. Important Details OS : Windows Text Editor : VScode I am using mingw64 and I run the Makefile with MinGW32-make What I tried The command that I putted on the terminal was: MinGW32-make… Read More How to use if and else statement in a Makefile – Windows?

I have a Makefile in which I would like to run several commands and ignore error. However, the make target will fail if one of the commands fail. I am running this Makefile on Mac, Ubuntu, and Redhat, so the versions of make are different. I believe the lowest version is 3.8. Currently, my solution… Read More Makefile: Execute several commands, ignore errors and return exit code

Folks, I need some help in understanding what’s happening, I do not see how to pass an option to g++ compiler in a makefile. If you can just try to reproduce my stuff and get me some info, it would be valuable (for me). Makefile content: MYCPPFLAGS := what a surprise %.o: %.cpp %.h g++… Read More g++ Flag variable not seen by make

environment os: macos 12.6.3 (intel) gnu make: 3.81 execute command: make -v get: GNU Make 3.81 Copyright (C) 2006 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. This program built for i386-apple-darwin11.3.0 steps The directory… Read More Why does the gnu make command default to compiling c files with the same name

I’m making an FTP server from scratch in C. I need a makefile to compile. his is the architecture of my project : / include / header file (*.h) src / potential sub directories / *.c *.c main.c Makefile this is my makefile : SRC := main.c $(wildcard src/*.c) $(wildcard src/**/*.c) OBJ := $(SRC:%.c=obj/%.o) DEP… Read More make: *** No rule to make target 'obj/main.o', needed by 'myftp'. Stop