I’m developing a simple buffering system in VHDL. I get the error I mentioned in the title for "empty" whenever I try to compile. I don’t know why it won’t let me invert a std_logic type. I’ve also been getting errors about the comparisons. For some reason, it doesn’t recognize the ">" and "<" operators on status_as_int and the thresholds.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY Buffer_Controller is
port (
empty : in std_logic;
full : in std_logic;
filling_status : in std_logic_vector(14 downto 0);
read_thresh : in integer;
write_thresh : in integer;
read_now : out std_logic;
write_now : out std_logic
);
END ENTITY;
ARCHITECTURE ctrl of Buffer_Controller is
signal status_as_int : integer;
BEGIN
status_as_int <= to_integer(unsigned(filling_status));
read_now <= '1' when (NOT(empty) AND status_as_int > read_thresh) else
'0';
write_now <= '1' when (NOT(full) AND status_as_int < write_thresh) else
'0';
END ARCHITECTURE;
>Solution :
empty and full are not booleans. They’re std_logic, which is a user defined type (defined in the ieee.std_logic_1164 library). That’s not a boolean.
Yes, you can invert them, but the result will still be std_logic. (The overloaded implementation of NOT for std_logic is also defined in the ieee.std_logic_1164 library).
To convert to boolean, You need to compare them to something that can be interpreted as std_logic, e.g.
read_now <= '1' when
empty = '0' AND
status_as_int > read_thresh
else '0';